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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCIDR1, ID Register 1</h1><p>The TRCIDR1 characteristics are:</p><h2>Purpose</h2>
        <p>Returns the tracing capabilities of the trace unit.</p>
      <h2>Configuration</h2><p>External register TRCIDR1 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-trcidr1.html">TRCIDR1[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCIDR1 are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRCIDR1 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="8"><a href="#fieldset_0-31_24">DESIGNER</a></td><td class="lr" colspan="8"><a href="#fieldset_0-23_16">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">RES1</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">TRCARCHMAJ</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">TRCARCHMIN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">REVISION</a></td></tr></tbody></table><h4 id="fieldset_0-31_24">DESIGNER, bits [31:24]</h4><div class="field">
      <p>Indicates which company designed the trace unit. The permitted values of this field are the same as <a href="AArch64-midr_el1.html">MIDR_EL1</a>.Implementer.</p>
    </div><h4 id="fieldset_0-23_16">Bits [23:16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_12">Bits [15:12]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-11_8">TRCARCHMAJ, bits [11:8]</h4><div class="field">
      <p>Major architecture version.</p>
    <table class="valuetable"><tr><th>TRCARCHMAJ</th><th>Meaning</th></tr><tr><td class="bitfield">0b1111</td><td>
          <p>If both TRCARCHMAJ and TRCARCHMIN == <span class="hexnumber">0xF</span> then refer to <a href="ext-trcdevarch.html">TRCDEVARCH</a>.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field reads as <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-7_4">TRCARCHMIN, bits [7:4]</h4><div class="field">
      <p>Minor architecture version.</p>
    <table class="valuetable"><tr><th>TRCARCHMIN</th><th>Meaning</th></tr><tr><td class="bitfield">0b1111</td><td>
          <p>If both TRCARCHMAJ and TRCARCHMIN == <span class="hexnumber">0xF</span> then refer to <a href="ext-trcdevarch.html">TRCDEVARCH</a>.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field reads as <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-3_0">REVISION, bits [3:0]</h4><div class="field"><p>Implementation revision.</p>
<p>Returns an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value that identifies the revision of the trace unit.</p>
<p>Arm deprecates any use of this field and recommends that implementations set this field to zero.</p></div><h2>Accessing TRCIDR1</h2><h4>TRCIDR1 can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>ETE</td><td><span class="hexnumber">0x1E4</span></td><td>TRCIDR1</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When OSLockStatus() or !IsTraceCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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